1. Field of the Invention
The present invention relates to a method of switching a clock signal between duplexed clock signals for supplying the clock signal stably to a duplexed information processing apparatus or a synchronous communication apparatus, and a clock signal generator to be used therefor.
2. Description of the Related Art
A duplexed clock switching system of this type has been developed with duplexed clock signal generators which are essential to the system for switching from one to another clock signal generator at stand-by when the operation is interrupted due to trouble or maintenance of the clock signal generator in use in order to supply clock signals continuously so that the operation will not be interrupted. Various kinds of systems have been disclosed.
For example, in Japanese Patent Laid-open No. 2-134022/1990 or Japanese Patent Laid-open No. 2-159611/1990, there are disclosed plans for providing a duplexed clock signal generator system by employing a crystal oscillator of high precision as a reference oscillator and outputting a signal generated by the reference oscillator and a signal produced by dividing this generated signal through a stable phase locked-loop oscillator (PLL Oscillator).
Also, in Japanese Patent Laid-open No. 59-31668/1984 or Japanese Patent Laid-open No. 62-169560/1987, there are disclosed systems which include two clock signal generating apparatus each comprising an independent clock signal generator which switch between clock signals outputted from one clock signal generator to clock signals outputted from the other clock signal generator and supplies the clock signals to each device, depending on the case.
Further, a transient free clock switch logic is disclosed in U.S. Pat. No. 4,899,351 for precluding a mixed state of both clock signals and making only one signal valid when switching from one duplexed clock signal generator to the other.
A conventional duplexed apparatus in which each of these clock signal generators are provided independently will next be described with reference to FIG. 1.
The duplexed apparatus of FIG. 1 is structured with a pair of processor systems 20, 21, each system having an independent oscillator 201 (211) for producing clock signals. Inasmuch as these two processor systems 20, 21 are of symmetrical structure to each other, one system 20 will be described below with the parts of the other system 21 indicated in parentheses ( ).
The processor system 20 (21) comprises the oscillator 201 (211); a clock gate 208 (218) which receives clock signals from its own oscillator 201 (211); a clock gate 209 (219) for receiving clock signals from the oscillator 211 (201) of the other system; a clock selection circuit, i.e., a switching circuit 203 (213) which receives output signals from two clock gates 208, 209 (218, 219) and outputs one of the received output signals; a clock selection logic circuit 204 (214) which monitors clock signals from the oscillators of the two systems 20, 21 and controls the opening/closing operation of clock gates 208, 209 (218, 219) and switching operation of clock signals to be outputted from the clock selection circuit 203 (213) according to the selected clock signal; a distribution circuit 207 (217) which receives an output signal from the clock selection circuit 203 (213); and a logic circuit 205 (215).
In a duplexed apparatus, the same clock signal is generally used in both apparatus. Therefore, when clock signals from oscillator 201 are selected, processor 20 opens its own clock gate 208 and processor 21 opens clock gate 219 which is connected to the other processor 20, and clock signals are supplied from oscillator 201 to both distribution circuits 207, 217 and the circuits disposed downstream therefrom. For switching the oscillator from 201 to 211, clock selection circuits 203, 213 are controlled by the clock selection logic circuits 204, 214 for switching, and clock gates 208, 219 are closed and clock gates 209, 218 are opened, respectively.
In the duplexed apparatus shown in FIG. 2, the two apparatus 40, 41 do not have the clock gate 208 and the like included in the apparatus shown in FIG. 1. Instead, each apparatus 40, 41 has a clock switching circuit 403, 413 for directly receiving output signals from its own oscillator and the other apparatus, and further, PLL circuits 406,416 are provided as phase synchronization means between circuits 403, 413 and the distribution circuits 407,417, respectively.
In each of the above conventional apparatus with a duplexed clock, when the frequency of the signal generated by one reference oscillator is divided by means such as a PLL circuit for duplicating the clock signal as shown in Japanese Patent Laid-open No. 2-134022/1990, no phase discrepancy of the clock signal occurs before or after switching of the clock. However, if there is a problem with the only reference oscillator provided, the apparatus cannot work as a duplexed apparatus, and therefore, the duplexing means of the above apparatus is not sufficient as a preventive measure against trouble.
Also, in the case of FIG. 1 and FIG. 2 in which oscillators are perfectly duplexed, as shown in the timing charts illustrated in FIG. 3 or FIG. 4, the pulse width may extend or the clock cycle may be shortened or lengthened at the time of switching the clock, thereby causing omission or variation in frequency of the pulse.
When the processor is duplexed, it is often necessary to establish synchronization between the two apparatus. Therefore, if there is fluctuation between clocks which are supplied to each apparatus, regular operation of the whole apparatus is not secure and hence, defective operation becomes unavoidable due to switching of the clock.